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ST1S10
3 A, 900 kHz, monolithic synchronous step-down regulator
Features

Step-down current mode PWM regulator Output voltage adjustable from 0.8 V Input voltage from 2.5 V up to 18 V 2% DC output voltage tolerance Synchronous rectification Inhibit function Synchronizable switching frequency from 400 kHz up to 1.2 MHz Internal soft start Dynamic short circuit protection Typical efficiency: 90% 3 A output current capability Stand-by supply current: max 6 A over temperature range Operative junction temp: from -25C to 125C
DFN8 (4x4mm) PowerSO-8
Description
The ST1S10 is a high efficiency step-down PWM current mode switching regulator capable of providing up to 3 A of output current. The device operates with an input supply range from 2.5 V to 18 V and provides an adjustable output voltage from 0.8 V (VFB) to 0.85*VIN_SW [VOUT = VFB*(1+R1/R2)]. It operates either at a 900 kHz fixed frequency or can be synchronized to an external clock (from 400 kHz to 1.2 MHz). The high switching frequency allows the use of tiny SMD external components, while the integrated synchronous rectifier eliminates the need for a Schottky diode. The ST1S10 provides excellent transient response, and is fully protected against thermal overheating, switching over-current and output short circuit. The ST1S10 is the ideal choice for point-of-load regulators or LDO pre-regulation.
Applications
Consumer - STB, DVD, DVD recorders, TV, VCR, car audio, LCD monitors Networking - XDSL, modems, DC-DC modules Computer - Optical storage, HD drivers, printers, audio/graphic cards Industrial and security - Battery chargers, DC-DC converters, PLD, PLA, FPGA, LED drivers Device summary

Table 1.
Package Part number DFN8 (4x4 mm) ST1S10 ST1S10PUR PowerSO-8 ST1S10PHR
October 2007
Rev. 3
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Contents
ST1S10
Contents
1 2 3 4 5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output capacitor (VOUT > 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output capacitor (0.8 V < VOUT < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Inductor (VOUT > 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Inductor (0.8 V < VOUT < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Function operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.8.1 5.8.2 5.8.3 5.8.4 5.8.5 Sync operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OCP (over-current protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SCP (short circuit protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SCP and OCP operation with high capacitive load . . . . . . . . . . . . . . . . 12
6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 8 9 10
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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ST1S10
Application circuit
1
Figure 1.
Application circuit
Typical application circuit
L1 3.3H 12V
VIN_SW SW
5V - 3A
C1 4.7F
EN VIN_A
ST1S10
FB
R1 C2 22F R2
C3 0.1F
SYNC AGND PGND
3/26
Pin configuration
ST1S10
2
Figure 2.
Pin configuration
Pin connections (top view for PowerSO-8, bottom view for DFN8)
DFN8 (4x4)
PowerSO-8
Table 2.
Pin n 1 2 3 4 5 6 7 8 epad
Pin description
Symbol VIN_A INH (EN) VFB AGND SYNC VIN_SW SW PGND epad Name and function Analog input supply voltage to be tied to VIN supply source Inhibit pin active low. Connect to VIN_A if not used Feedback voltage for connection to external voltage divider to set the VOUT from 0.8V up to 0.85*VIN_SW. (see output voltage selection paragraph 5.5) Analog ground Synchronization and frequency select. Connect SYNC to GND for 900 kHz operation, or to an external clock from 400 kHz to 1.2 MHz. (see Sync operation paragraph 5.8.1) Power input supply voltage to be tied to VIN power supply source Switching node to be connected to the inductor Power ground Exposed pad to be connected to ground
4/26
ST1S10
Maximum ratings
3
Table 3.
Maximum ratings
Absolute maximum ratings
Parameter Positive power supply voltage Positive supply voltage Inhibit voltage Output switch voltage Feedback voltage FB current Synchronization Storage temperature range Operating junction temperature range Value -0.3 to 20 -0.3 to 20 -0.3 to VIN_A -0.3 to 20 -0.3 to 2.5 -1 to +1 -0.3 to 6 -40 to 150 -25 to 125 Unit V V V V V mA V C C
Symbol VIN_SW VIN_A VINH VSW VFB IFB Sync TSTG TOP
Note:
Absolute maximum ratings are the values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Thermal data
Parameter Thermal resistance junction-ambient Thermal resistance junction-case PowerSO-8 40 12 DFN8 40 4 Unit C/W C/W
Table 4.
Symbol RthJA RthJC
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Electrical characteristics
ST1S10
4
Table 5.
Electrical characteristics
Electrical characteristics VIN = VIN_SW = VIN_A = VINH = 12 V, VSYNC = GND, VOUT = 5 V, IOUT = 10 mA, CIN = 4.7 F +0.1 F, COUT = 22 F, L1 = 3.3 H, TJ = -25 to 125C (Unless otherwise specified, refer to the typical application circuit. Typical values assume TJ = 25C)
Parameter Feedback voltage VFB pin bias current Quiescent current Output current (1) VINH > 1.2 V, not switching VINH < 0.4 V VIN = 2.5 V to 18 V VOUT = 0.8 V to 13.6 V (2) Device ON VINH IINH Inhibit threshold Device OFF Inhibit pin current 2.5 V < VIN < 18 V 10 mA < IOUT < 3 A VFB = 0.7 V, Sync = GND TJ = 25C 0.7 85 ISW = 750 mA ISW = 750 mA 2 0.4 0.5 0.9 90 0.10 0.12 5.0 IOUT = 100 mA to 300 mA IOUT = 300 mA to 3 A Thermal shut down Thermal shut down hysteresis 100 mA < IOUT < 1 A, tR = tF 500 ns 10 mA < IOUT < short VIN = 2.5 V to 18 V, VSYNC = 0 to 5 V VIN = 2.5 V to 18 V VIN = 2.5 V to 18 V VIN = 2.5 V to 18 V 1.6 0.4 250 0.4 85 90 150 15 5 10 1.2 1.1 0.4 V A %VOUT/ VIN %VOUT/ IOUT MHz % A % % C C %VO %VO MHz ns V V 3.0 1.2 1.5 2 Test conditions TJ = 25C TJ = -25C to 125C Min. 784 776 Typ. 800 800 Max. 816 824 600 2.5 6 Unit mV mV nA mA A A V
Symbol VFB IFB IQ IOUT
%VOUT/VIN Reference line regulation %VOUT/ IOUT PWM fs DMAX RDSon-N RDSon-P ISWL TSHDN THYS Reference load regulation PWM switching frequency Maximum duty cycle (2) NMOS switch on resistance PMOS switch on resistance Switch current limitation Efficiency
VOUT/IOUT Output transient response VOUT/IOUT Short circuit removal response @IO=short (overshot) FSYNC SYNCWD VIL_SYNC VIH_SYNC SYNC frequency capture range SYNC pulse width SYNC input threshold low SYNC input threshold high
6/26
ST1S10 Table 5.
Electrical characteristics Electrical characteristics (continued) VIN = VIN_SW = VIN_A = VINH = 12 V, VSYNC = GND, VOUT = 5 V, IOUT = 10 mA, CIN = 4.7 F +0.1 F, COUT = 22 F, L1 = 3.3 H, TJ = -25 to 125C (Unless otherwise specified, refer to the typical application circuit. Typical values assume TJ = 25C)
Parameter SYNC input current Test conditions VIN = 2.5 V to 18 V, VSYNC = 0 or 5 V VIN rising Hysteresis Min. -10 2.3 200 Typ. Max. +10 Unit A V mV
Symbol IIL, IIH UVLO
Under voltage lock-out threshold
1. Guaranteed by design, but not tested in production. 2. See output voltage selection paragraph 5.5 for maximum duty cycle conditions.
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Application information
ST1S10
5
5.1
Application information
Description
The ST1S10 is a high efficiency synchronous step-down DC-DC converter with inhibit function. It provides up to 3 A over an input voltage range of 2.5 V to 18 V, and the output voltage can be adjusted from 0.8 V up to 85% of the input voltage level. The synchronous rectification removes the need for an external Schottky diode and allows higher efficiency even at very low output voltages. A high internal switching frequency (0.9 MHz) allows the use of tiny surface-mount components, as well as a resistor divider to set the output voltage value. In typical application conditions, only an inductor and 3 capacitors are required for proper operation. The device can operate in PWM mode with a fixed frequency or synchronized to an external frequency through the SYNC pin. The current mode PWM architecture and stable operation with low ESR SMD ceramic capacitors results in low, predictable output ripple. No external compensation is needed. To maximize power conversion efficiency, the ST1S10 works in pulse skipping mode at light load conditions and automatically switches to PWM mode when the output current increases. The ST1S10 is equipped with thermal shut down protection activated at 150C (typ.). Cycle-by-cycle short circuit protection provides protection against shorted outputs for the application and the regulator. An internal soft start for start-up current limiting and power ON delay of 275 s (typ.) helps to reduce inrush current during start-up.
5.2
5.2.1
External components selection
Input capacitor
The ST1S10 features two VIN pins: VIN_SW for the power supply input voltage where the switching peak current is drawn, and VIN_A to supply the ST1S10 internal circuitry and drivers. The VIN_SW input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the IC. A high power supply source impedance requires larger input capacitance. For the VIN_SW input capacitor the RMS current rating is a critical parameter that must be higher than the RMS input current. The maximum RMS input current can be calculated using the following equation:
I RMS
= IO D - 2 D + D
2
2
where is the expected system efficiency, D is the duty cycle and IO is the output DC current. The duty cycle can be derived using the equation: D = (VOUT + VF) / (VIN-VSW) where VF is the voltage drop across the internal NMOS, and VSW represents the voltage drop across the internal PDMOS. The minimum duty cycle (at VIN_max) and the maximum
8/26
ST1S10
Application information duty cycle (at VIN_min) should be considered in order to determine the max IRMS flowing through the input capacitor. A minimum value of 4.7 F for the VIN_SW and a 0.1 F ceramic capacitor for the VIN_A are suitable in most application conditions. A 10 F or higher ceramic capacitor for the VIN_SW and a 1 F or higher for the VIN_A are recommended in cases of higher power supply source impedance or where long wires are needed between the power supply source and the VIN pins. The above higher input capacitor values are also recommended in cases where an output capacitive load is present (47 F < CLOAD < 100 F), which could impact the switching peak current drawn from the input capacitor during the start-up transient. In cases of very high output capacitive loads (CLOAD > 100 F), all input/output capacitor values shall be modified as described in the OCP and SCP operation section 5.8.5 of this document. The input ceramic capacitors should have a voltage rating in the range of 1.5 times the maximum input voltage and be located as close as possible to VIN pins.
5.3
Output capacitor (VOUT > 2.5 V)
The most important parameters for the output capacitor are the capacitance, the ESR and the voltage rating. The capacitance and the ESR affect the control loop stability, the output ripple voltage and transient response of the regulator. The ripple due to the capacitance can be calculated with the following formula: VRIPPLE(C) = (0.125 x ISW) / (FS x COUT) where FS is the PWM switching frequency and ISW is the inductor peak-to-peak switching current, which can be calculated as: ISW = [(VIN - VOUT) / (FS x L)] x D where D is the duty cycle. The ripple due to the ESR is given by: VRIPPLE(ESR) = ISW x ESR The equations above can be used to define the capacitor selection range, but final values should be verified by testing an evaluation circuit. Lower ESR ceramic capacitors are usually recommended to reduce the output ripple voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower output ripple voltage. Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors usually have very low ESL, making ripple voltages due to the ESL negligible. In order to reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection paths should be kept as short as possible. The ST1S10 has been designed to perform best with ceramic capacitors. Under typical application conditions a minimum ceramic capacitor value of 22 F is recommended on the output, but higher values are suitable considering that the control loop has been designed to work properly with a natural output LC frequency provided by a 3.3 H inductor and 22 F output capacitor. If the high capacitive load application circuit shown in Figure 3 is used, a 47 F (or 2 x 22 F capacitors in parallel) could be needed as described in the OCP and SCP operation section 5.8.5. of this document.
9/26
Application information
ST1S10
The use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum output voltage is recommended.
5.4
Output capacitor (0.8 V < VOUT < 2.5 V)
For applications with lower output voltage levels (Vout < 2.5 V) the output capacitance and inductor values should be selected in a way that improves the DC-DC control loop behavior. In this output condition two cases must be considered: VIN > 8 V and VIN < 8 V. For VIN < 8 V the use of 2 x 22 F capacitors in parallel to the output is recommended, as shown in Figure 4. For VIN > 8 V, a 100 F electrolytic capacitor with ESR < 0.1 should be added in parallel to the 2 x 22 F output capacitors as shown in Figure 5.
5.5
Output voltage selection
The output voltage can be adjusted from 0.8 V up to 85% of the input voltage level by connecting a resistor divider (see R1 and R2 in the typical application circuit) between the output and the VFB pin. A resistor divider with R2 in the range of 20 k is a suitable compromise in terms of current consumption. Once the R2 value is selected, R1 can be calculated using the following equation: R1 = R2 x (VOUT - VFB) / VFB where VFB = 0.8 V (typ.). Lower values are suitable as well, but will increase current consumption. Be aware that duty cycle must be kept below 85% at all application conditions, so that: D = (VOUT + VF) / (VIN-VSW) < 0.85 where VF is the voltage drop across the internal NMOS, and VSW represents the voltage drop across the internal PDMOS. Note that once the output current is fixed, higher VOUT levels increase the power dissipation of the device leading to an increase in the operating junction temperature. It is recommended to select a VOUT level which maintains the junction temperature below the thermal shut-down protection threshold (150C typ.) at the rated output current. The following equation can be used to calculate the junction temperature (TJ): TJ = {[VOUT x IOUT x RthJA x (1-)] / } +TAMB where RthJA is the junction-to-ambient thermal resistance, is the efficiency at the rated IOUT current and TAMB is the ambient temperature. To ensure safe operating conditions the application should be designed to keep TJ < 140C.
5.6
Inductor (VOUT > 2.5 V)
The inductor value fixes the ripple current flowing through output capacitor and switching peak current. The ripple current should be kept in the range of 20-40% of IOUT_MAX (for example it is 0.6 - 1.2 A at IOUT = 3 A). The approximate inductor value can be obtained with the following formula: L = [(VIN - VOUT) / ISW] x TON
10/26
ST1S10 where TON is the ON time of the internal switch, given by: TON = D/FS
Application information
The inductor should be selected with saturation current (ISAT) equal to or higher than the inductor peak current, which can be calculated with the following equation: IPK = IO + (ISW/2), ISAT IPK The inductor peak current must be designed so that it does not exceed the switching current limit.
5.7
Inductor (0.8 V < VOUT < 2.5 V)
For applications with lower output voltage levels (Vout < 2.5 V) the description in the previous section is still valid but it is recommended to keep the inductor values in a range from 1H to 2.2 H in order to improve the DC-DC control loop behavior, and increase the output capacitance depending on the VIN level as shown in the Figure 4 and Figure 5. In most application conditions a 2.2 H inductor is the best compromise between DC-DC control loop behavior and output voltage ripple.
5.8
5.8.1
Function operation
Sync operation
The ST1S10 operates at a fixed frequency or can be synchronized to an external frequency with the SYNC pin. The ST1S10 switches at a frequency of 900 kHz when the SYNC pin is connected to ground, and can synchronize the switching frequency between 400 kHz to 1.2 MHz from an external clock applied to the SYNC pin. When the SYNC feature is not used, this pin must be connected to ground with a path as short as possible to avoid any possible noise injected in the SYNC internal circuitry.
5.8.2
Inhibit function
The inhibit pin can be used to turn OFF the regulator when pulled down, thus drastically reducing the current consumption down to less than 6 A. When the inhibit feature is not used, this pin must be tied to VIN to keep the regulator output ON at all times. To ensure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section under VINH. Any slew rate can be used to drive the inhibit pin.
5.8.3
OCP (over-current protection)
The ST1S10 DC-DC converter is equipped with a switch over-current protection. In order to provide protection for the application and the internal power switches and bonding wires, the device goes into a shutdown state if the switch current limit is reached and is kept in this condition for the TOFF period (TOFF(OCP) = 135 s typ.) and turns on again for the TON period (TON(OCP) = 22 s typ.) under typical application conditions. This operation is repeated cycle by cycle. Normal operation is resumed when no over-current is detected.
11/26
Application information
ST1S10
5.8.4
SCP (short circuit protection)
In order to protect the entire application and reduce the total power dissipation during an overload or an output short circuit condition, the device is equipped with dynamic short circuit protection which works by internally monitoring the VFB (feedback voltage). In the event of an overload or output short circuit, if the VOUT voltage is reduced causing the feedback voltage (VFB) to drop below 0.3 V (typ.), the device goes into shutdown for the TOFF time (TOFF(SCP) = 288 s typ.) and turns on again for the TON period (TON(SCP) = 130 s typ.). This operation is repeated cycle by cycle, and normal operation is resumed when no overload is detected (VFB > 0.3 V typ.) for the full TON period. This dynamic operation can greatly reduce the power dissipation in overload conditions, while still ensuring excellent power-on startup in most conditions.
5.8.5
SCP and OCP operation with high capacitive load
Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from short circuit and overload. However, a highly capacitive load on the output may cause difficulties during start-up. This can be resolved by using the modified application circuit shown in Figure 3, in which a minimum of 10 F for C1 and a 4.7 F ceramic capacitor for C3 are used. Moreover, for CLOAD > 100 F, it is necessary to add the C4 capacitor in parallel to the upper voltage divider resistor (R1) as shown in Figure 3. The recommended value for C4 is 4.7 nF. Note that C4 may impact the control loop response and should be added only when a capacitive load higher than 100 F is continuously present. If the high capacitive load is variable or not present at all times, in addition to C4 an increase in the output ceramic capacitor C2 from 22 F to 47 F (or 2 x 22 F capacitors in parallel) is recommended. Also in this case it is suggested to further increase the input capacitors to a minimum of 10 F for C1 and a 4.7 F ceramic capacitor for C3 as shown in Figure 3.
Figure 3.
Application schematic for heavy capacitive load
L1 3.3H 12V
VIN_SW SW
C4 (*) 4.7nF
5V - 3A
C1 10F
EN VIN_A
ST1S10
FB
R1 C2(*) 22F R2
Output Load LOAD
CLOAD
C3 4.7F
SYNC AGND PGND
(*) see OCP and SCP descriptions for C2 and C4 selection
12/26
ST1S10
Application information
Figure 4.
Application schematic for low output voltage (VOUT < 2.5 V) and 2.5 V < VIN < 8 V
L1 2.2H VIN<8V
VIN_SW SW
0.8VC1 10F
EN VIN_A
ST1S10
FB
R1 C2 2x22F R2
C3 0.1F
SYNC AGND PGND
Figure 5.
Application schematic for low output voltage (VOUT < 2.5 V) and 8 V < VIN < 16 V
L1 2.2H 8VVIN_SW SW
0.8VFB
C1 10F
EN VIN_A
ST1S10
2x22F R2
C3 4.7F
SYNC AGND PGND
C5 100F Electrolytic ESR<0.1Ohm
13/26
Layout considerations
ST1S10
6
Layout considerations
Layout is an important step in design for all switching power supplies. High-speed operation (900 kHz) of the ST1S10 device demands careful attention to PCB layout. Care must be taken in board layout to get device performance, otherwise the regulator could show poor line and load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor must be placed as close as possible to the IC pins as well as the inductor and output capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to minimize the effects of ground noise. Connect these ground nodes together underneath the device and make sure that small signal components returning to the AGND pin and do not share the high current path of CIN and COUT. The feedback voltage sense line (VFB) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring connected to the ground.
Figure 6.
PCB layout suggestion
VFB guard-ring
CN1=Input power supply CN2=Enable/Disable CN3=Input sync. CN4=VOUT
39mm
Input capacitor C1 must be placed as close as possible to the IC pins as well as the inductor L1 and output capacitor C2
Vias from thermal pad to bottom layer
47mm
14/26
ST1S10
Layout considerations
Figure 7.
PCB layout suggestion
Common ground node for power ground
Power Ground
I IOUT
IIN
6.1
Thermal considerations
The leadframe die pad, of ST1S10, is exposed at the bottom of the package and must be soldered directly to a properly designed thermal pad on the PCB, the addition of thermal vias from the thermal pad to an internal ground plane will help increase power dissipation.
15/26
Diagram
ST1S10
7
Figure 8.
Diagram
Block diagram
16/26
ST1S10
Typical performance characteristics
8
Typical performance characteristics
Unless otherwise specified, refer to the typical application circuit under the following conditions: TJ = 25C, VIN = VIN-SW = VIN-A = VINH = 12 V, VSYNC = GND, VOUT = 5 V, IOUT = 10 mA, CIN = 4.7 F + 0.1 F, COUT = 22 F, L1 = 3.3 H Voltage feedback vs. temperature Figure 10. Oscillator frequency vs. temperature
Figure 9.
830 810
VFB [mV]
Frequency [MHz]
1.2 1.1 1 0.9 0.8 0.7 0.6 -50
VIN-A=VIN-SW=VINH=12V, VFB=0V
820 800 790 780 770 760
-50 -25 0 25 50 75 100 125
VIN=VINH=12V, VOUT=0.8V, IOUT=10mA
-25
0
25
50
75
100
125
TEMPERATURE [C]
TEMPERATURE [C]
Figure 11. Max duty cycle vs. temperature
Figure 12. Inhibit threshold vs. temperature
1.4 1.2 1
VINH (V)
92
Duty Cycle [%]
90 88 86 84 82 80 -50 -25 0 25 50 75 100 125
VIN-A=VIN-SW=VINH=12V, VFB=0V
0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125
VIN-A=VIN-SW=2.5V, VOUT=0.8V, IOUT=10mA
TEMPERATURE [C]
TEMPERATURE [C]
Figure 13. Reference line regulation vs. temperature
Figure 14. Reference load regulation vs. temperature
0.2
Line [%(V OUT /VIN)]
1.3
Load [%VOUT /I OUT ]
VIN-A=VIN-SW=VINH=12V, IOUT from 10mA to 3A
0.1 0 -0.1
VIN-A=VIN-SW=VINH from 2.5 to 20V, VOUT=0.8V, IOUT=10mA
1 0.7 0.4 0.1 -0.2 -0.5 -25 0 25 50 75 100 125
-0.2 -50
-25
0
25
50
75
100
125
TEMPERATURE [C]
TEMPERATURE [C]
17/26
Typical performance characteristics
ST1S10
Figure 15. ON mode quiescent current vs. temperature
Figure 16. Shutdown mode quiescent current vs. temperature
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50
7 6 5
IQ (A)
VIN-A=VIN-SW=12V, VINH=GND, VOUT=0.8V
IQ (mA)
4 3 2 1 0
VIN-A=VIN-SW=12V, VINH=1.2V, VOUT=0.8V
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE [C]
TEMPERATURE [C]
Figure 17. PMOS ON resistance vs. temperature
Figure 18. NMOS ON resistance vs. temperature
320 270 RDSON-P[m ]
RDSON-N[m ]
VIN=12V, ISW=750mA
120 110 100 90 80 70 60 50 -50
VIN=12V, ISW=750mA
220 170 120 70 20 -50 -25 0 25 50 75 100 125
-25
0
25
50
75
100
125
TEMPERATURE [C]
TEMPERATURE [C]
Figure 19. Efficiency vs. temperature
Figure 20. Efficiency vs. output current
100
EFFICIENCY [%]
100 EFFICIENCY [%]
VIN-A=VIN-SW=VINH=12V, VOUT=5V, IOUT=3A
90 80 70 60 50 -50
90 80 70 60
VIN-A=VIN-SW=VINH=12V, VOUT=5V, TJ=25C
-25
0
25
50
75
100
125
50 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT [A]
TEMPERATURE [C]
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ST1S10 Figure 21. Efficiency vs. output current
Typical performance characteristics Figure 22. Efficiency vs. output current
100
100
EFFICIENCY [%]
VIN-A=VIN-SW=VINH=5V, VOUT=3.3V, TJ=25C
EFFICIENCY [%]
90 80 70 60 50 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT [A]
90 80 70 60
VIN-A=VIN-SW=VINH=16V, VOUT=12V, TJ=25C
50 0 0.5 1 1.5 2 2.5 3
OUTPUT CURRENT [A]
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Package mechanical data
ST1S10
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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ST1S10
Package mechanical data
PowerSO-8 mechanical data
Dim. A A1 A2 b c D D1 E E1 E2 e h L k ccc 0.25 0.40 0 0.00 1.25 0.31 0.17 4.80 2.24 5.80 3.80 1.55 4.90 3.10 6.00 3.90 2.41 1.27 0.50 1.27 8 0.10 0.010 0.016 0 0.51 0.25 5.00 3.20 6.20 4.00 2.51 mm. Min. Typ. Max. 1.70 0.15 0.00 0.049 0.012 0.007 0.189 0.088 0.228 0.150 0.061 0193 0.122 0.236 0.154 0.095 0.050 0.020 0.050 8 0.004 Min. inch. Typ. Max. 0.067 0.006 0.142 0.020 0.010 0.197 0.126 0.244 0.157 0.099
7195016C
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Package mechanical data
ST1S10
DFN8 (4x4) mechanical data
mm. Dim. Min. A A1 A3 b D D2 E E2 e L 0.40 0.23 3.90 2.82 3.90 2.05 0.80 0 Typ. 0.90 0.02 0.20 0.30 4.00 3.00 4.00 2.20 0.80 0.50 0.60 0.016 0.38 4.10 3.23 4.10 2.30 0.009 0.154 0.111 0.154 0.081 Max. 1.00 0.05 Min. 0.031 0 Typ. 0.035 0.001 0.008 0.012 0.157 0.118 0.157 0.087 0.031 0.020 0.024 0.015 0.161 0.127 0.161 0.091 Max. 0.039 0.002 inch.
7869653B
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ST1S10
Package mechanical data
Tape & reel SO-8 mechanical data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 8.1 5.5 2.1 3.9 7.9 12.8 20.2 60 22.4 8.5 5.9 2.3 4.1 8.1 0.319 0.216 0.082 0.153 0.311 Typ. Max. 330 13.2 0.504 0.795 2.362 0.882 0.335 0.232 0.090 0.161 0.319 Min. Typ. Max. 12.992 0.519 inch.
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Package mechanical data
ST1S10
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 4.35 4.35 1.1 4 8 12.8 20.2 99 101 14.4 0.171 0.171 0.043 0.157 0.315 Typ. Max. 330 13.2 0.504 0.795 3.898 3.976 0.567 Min. Typ. Max. 12.992 0.519 inch.
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ST1S10
Revision history
10
Table 6.
Date
Revision history
Document revision history
Revision 1 2 3 Initial release. Add RthJC on Table 4. Added new paragraph 6: Layout considerations. Changes
28-Aug-2007 24-Sep-2007 25-Oct-2007
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ST1S10
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